Project Release: FPGA as TI Link cable. (Verilog)

[nyancat]

Use an FPGA to link your computer with your TI calculator. Faster than TI cables, MIT license.

It is written in verilog and does not use vendor libraries, therefore it should work on pretty much any dev board that can do 3.3v. I've developed this with an iCEstick and a TinyFPGA BX using the yosys+nextpnr stack.

It's been tested on ti89 and v200 as they're the ones I have. It seems no less reliable than the grey and silver cables I have, and dramatically faster.

https://github.com/rvalles/dbus_ti_link_uart_verilog

Please give it a try if you're able.

[Wistaro]

Very interesting! Thanks for sharing

I'm wondering if it would be possible to do the same for the TI-8X serie, that uses the TI-GraphLink.

[nyancat]

Very interesting! Thanks for sharing

Thank you.

I'm wondering if it would be possible to do the same for the TI-8X serie, that uses the TI-GraphLink.

It should. While I don't own one (yet), they likely maintain the bus with 3.3v pullups too. I'd suggest to check with a multimeter before you plug anything, as 5v would fry your average FPGA 3.3v i/o pin.

If you're in a position where you can try this (that is, if you've got a FPGA devboard and understand it), it'd be very nice if you could. If anything, I'm quite curious about what transfer speeds these calculators would achieve with this.

I suspect that, at worst, you'd have to lower the dbus clock, which is a parameter in the Makefile, to something more reasonable.

[Lionel Debroux]

I missed this board's instance of that topic

TI-Z80 calculators do indeed use 5V on the legacy I/O port, and TI-68k calculators using 3.3V tolerate (and interoperate with) 5V calculators.

[lychniscuddly]

It would be great if you could give this a go if you're in a position to do so (that is, if you have an FPGA devboard and understand it). I'm really quite interested to see what transfer speeds these calculators might accomplish with this.