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Catégorie :Category: nCreator TI-Nspire
Auteur Author: no_name0908
Type : Classeur 3.0.1
Page(s) : 1
Taille Size: 2.98 Ko KB
Mis en ligne Uploaded: 17/04/2025 - 03:22:13
Uploadeur Uploader: no_name0908 (Profil)
Téléchargements Downloads: 2
Visibilité Visibility: Archive publique
Shortlink : http://ti-pla.net/a4586875
Type : Classeur 3.0.1
Page(s) : 1
Taille Size: 2.98 Ko KB
Mis en ligne Uploaded: 17/04/2025 - 03:22:13
Uploadeur Uploader: no_name0908 (Profil)
Téléchargements Downloads: 2
Visibilité Visibility: Archive publique
Shortlink : http://ti-pla.net/a4586875
Description
Fichier Nspire généré sur TI-Planet.org.
Compatible OS 3.0 et ultérieurs.
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1.) Inertial and Transport You can assign two types of delays within Verilog, Inertial and Transport. Inertial: Signal will assume its new value after a specified time delay if the signal is in the same state at least as long as the propogation delay. The default for the timing delay of a Verilog gate primitives is always zero. Rising and Falling edge delays can be specified during the primitive rise and fall operator. Inertial affectsgate type delays. Transport: Signal will assume its new value after the specified time delay. Affects the delays between operations such as wires. 2.) What two parts of synchronous/sequential design contain the Control Section and Data Section Synchronous Digital Design systems utilize a clock to synchronize the operation of all the flip flops, registers, and counters of the system. All changes occur immediately following the active clock edge and the clock period must be long enough so that all changes within the flip flops, registers and counters will have time to stabilize before the next active clock edge. MEaly and Moore machines typically for the control sections of the synchronous designs. 3.) What does Meta Stability do? Metastability: Can occur within digital systems when the data input to a flip flop is asynchronous to the clock, this can lead to hold or setup timing violations. It can cause flip flops to switch late or not at all, it can present a brief pulse at a flip flop oouput (runt pulse), cause flip flop oscillations, or can cause system failures. Metastability does not always cause a problem, If the data output signal resolves to a valid state before the next register captures the data then it does not negatively impact the system. If it does not resolve itself however then it can cause the system to fail. 4.) What does Flip Flop Hold Time do? The flip flop hold time ensures that the input must be stable for a certain amount of time after the active edge of the clock . The flip flop setup time ensures that is must be stable for a certain amount of time before the active edge of the clock cycle. 5.) What does a Clock Skew do? Clock Skew: The absolute time difference in the clock signal arrival between two points in the clock network and is often caused by delays in the interconnect within the clock distribution network. This can also be caused by the combinational logic used to select gates using the clock of certain devices. Positive Skew: Capturing the flip flop gets the clock delayed with reference to the launching flip flop. Negative Skew: launching the flip flop gets the clock delayed with reference to the capturing flip flop. 6.) What Does an en signal do? An en signal is a gate or a permission flag that controls whether a block of logic is active or not. 7.) What are two issues with hold time/setup time if they are not met? A violation of setp time can lead to the risk of metastability or incorrect sampling as the flip flop may capture the old value or a corrupted one. The metastability issue can lead to propagation issues with the flip flop. A violation of hold times can lead to inputs changing too soon after the clock edge, or it can lead to an inconsistent state that risks glitches or metastability issues once again. 8.) Make a Verilog Module with a 2 input AND gate with a delay of 2ns. module AND2_Delay ( input wire A, //First Input input wire B, //Second Input input wire C //Output ); and #2 inst ( .Y(Y), .A(A), .B(B) ); endmodule Made with nCreator - tiplanet.org
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Compatible OS 3.0 et ultérieurs.
<<
1.) Inertial and Transport You can assign two types of delays within Verilog, Inertial and Transport. Inertial: Signal will assume its new value after a specified time delay if the signal is in the same state at least as long as the propogation delay. The default for the timing delay of a Verilog gate primitives is always zero. Rising and Falling edge delays can be specified during the primitive rise and fall operator. Inertial affectsgate type delays. Transport: Signal will assume its new value after the specified time delay. Affects the delays between operations such as wires. 2.) What two parts of synchronous/sequential design contain the Control Section and Data Section Synchronous Digital Design systems utilize a clock to synchronize the operation of all the flip flops, registers, and counters of the system. All changes occur immediately following the active clock edge and the clock period must be long enough so that all changes within the flip flops, registers and counters will have time to stabilize before the next active clock edge. MEaly and Moore machines typically for the control sections of the synchronous designs. 3.) What does Meta Stability do? Metastability: Can occur within digital systems when the data input to a flip flop is asynchronous to the clock, this can lead to hold or setup timing violations. It can cause flip flops to switch late or not at all, it can present a brief pulse at a flip flop oouput (runt pulse), cause flip flop oscillations, or can cause system failures. Metastability does not always cause a problem, If the data output signal resolves to a valid state before the next register captures the data then it does not negatively impact the system. If it does not resolve itself however then it can cause the system to fail. 4.) What does Flip Flop Hold Time do? The flip flop hold time ensures that the input must be stable for a certain amount of time after the active edge of the clock . The flip flop setup time ensures that is must be stable for a certain amount of time before the active edge of the clock cycle. 5.) What does a Clock Skew do? Clock Skew: The absolute time difference in the clock signal arrival between two points in the clock network and is often caused by delays in the interconnect within the clock distribution network. This can also be caused by the combinational logic used to select gates using the clock of certain devices. Positive Skew: Capturing the flip flop gets the clock delayed with reference to the launching flip flop. Negative Skew: launching the flip flop gets the clock delayed with reference to the capturing flip flop. 6.) What Does an en signal do? An en signal is a gate or a permission flag that controls whether a block of logic is active or not. 7.) What are two issues with hold time/setup time if they are not met? A violation of setp time can lead to the risk of metastability or incorrect sampling as the flip flop may capture the old value or a corrupted one. The metastability issue can lead to propagation issues with the flip flop. A violation of hold times can lead to inputs changing too soon after the clock edge, or it can lead to an inconsistent state that risks glitches or metastability issues once again. 8.) Make a Verilog Module with a 2 input AND gate with a delay of 2ns. module AND2_Delay ( input wire A, //First Input input wire B, //Second Input input wire C //Output ); and #2 inst ( .Y(Y), .A(A), .B(B) ); endmodule Made with nCreator - tiplanet.org
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