322 Verilog Logic
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Catégorie :Category: nCreator TI-Nspire
Auteur Author: no_name0908
Type : Classeur 3.0.1
Page(s) : 1
Taille Size: 4.27 Ko KB
Mis en ligne Uploaded: 01/05/2025 - 22:20:22
Uploadeur Uploader: no_name0908 (Profil)
Téléchargements Downloads: 1
Visibilité Visibility: Archive publique
Shortlink : http://ti-pla.net/a4615096
Type : Classeur 3.0.1
Page(s) : 1
Taille Size: 4.27 Ko KB
Mis en ligne Uploaded: 01/05/2025 - 22:20:22
Uploadeur Uploader: no_name0908 (Profil)
Téléchargements Downloads: 1
Visibilité Visibility: Archive publique
Shortlink : http://ti-pla.net/a4615096
Description
Fichier Nspire généré sur TI-Planet.org.
Compatible OS 3.0 et ultérieurs.
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Transparent D Latch module d_latch(input D, input En, output reg Q); always @(*) begin if (En) Q = D; end endmodule SR LATCH module sr_latch(input S, input R, output reg Q); always @(*) begin if (S && ~R) Q = 1; else if (~S && R) Q = 0; // S = R = 0: retain state; S = R = 1: undefined end endmodule D FLIP FLOP module d_ff(input D, input clk, output reg Q); always @(posedge clk) begin Q <= D; end endmodule SR FLIP FLOP module sr_ff(input S, input R, input clk, output reg Q); always @(posedge clk) begin if (S && ~R) Q <= 1; else if (~S && R) Q <= 0; end endmodule TOGGLE FLIP FLOP module t_ff(input T, input clk, output reg Q); always @(posedge clk) begin if (T) Q <= ~Q; end endmodule SHIFT REGISTER 8BIT module shift_reg(input clk, input reset, input shift_en, input D, output reg [7:0] Q); always @(posedge clk or posedge reset) begin if (reset) Q <= 0; else if (shift_en) Q <= {Q[6:0], D}; end endmodule BINARY COUNTER 4BIT module binary_counter(input clk, input reset, output reg [3:0] count); always @(posedge clk or posedge reset) begin if (reset) count <= 0; else count <= count + 1; end endmodule BCD COUNTER 0-9 module bcd_counter(input clk, input reset, output reg [3:0] count); always @(posedge clk or posedge reset) begin if (reset) count <= 0; else if (count == 9) count <= 0; else count <= count + 1; end endmodule BINARY ADDER 4BIT module binary_adder(input [3:0] A, input [3:0] B, input Cin, output [3:0] Sum, output Cout); assign {Cout, Sum} = A + B + Cin; endmodule BINARY SUBTTRACTOR 4BIT module binary_subtractor(input [3:0] A, input [3:0] B, output [3:0] Diff, output Bout); assign {Bout, Diff} = A - B; endmodule N TO 1 MUX (EX 4 to 1) module mux4to1(input [3:0] in, input [1:0] sel, output reg out); always @(*) begin case (sel) 2'b00: out = in[0]; 2'b01: out = in[1]; 2'b10: out = in[2]; 2'b11: out = in[3]; endcase end endmodule M to 2^M DECODER (EX 2 to 4) module decoder2to4(input [1:0] in, output reg [3:0] out); always @(*) begin out = 4'b0000; out[in] = 1; end endmodule 2^m-to-m Priority Encoder module priority_encoder4to2(input [3:0] in, output reg [1:0] out); always @(*) begin casez (in) 4'b1???: out = 2'b11; 4'b01??: out = 2'b10; 4'b001?: out = 2'b01; 4'b0001: out = 2'b00; default: out = 2'b00; endcase end endmodule n-word x m-bit Synchronous ROM (example: 8x8) module sync_rom(input clk, input [2:0] addr, output reg [7:0] data); reg [7:0] memory [0:7] = {8'hAA, 8'hBB, 8'hCC, 8'hDD, 8'h11, 8'h22, 8'h33, 8'h44}; always @(posedge clk) begin data <= memory[addr]; end endmodule n-word x m-bit Asynchronous ROM (example: 8x8) module async_rom(input [2:0] addr, output [7:0] data); reg [7:0] memory [0:7] = {8'hAA, 8'hBB, 8'hCC, 8'hDD, 8'h11, 8'h22, 8'h33, 8'h44}; assign data = memory[addr]; endmodule n-word x m-bit Synchronous RAM (example: 8x8) module sync_ram(input clk, input we, input [2:0] addr, input [7:0] din, output reg [7:0] dout); reg [7:0] memory [0:7]; always @(posedge clk) begin if (we) memory[addr] <= din; dout <= memory[addr]; end endmodule Made with nCreator - tiplanet.org
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Compatible OS 3.0 et ultérieurs.
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Transparent D Latch module d_latch(input D, input En, output reg Q); always @(*) begin if (En) Q = D; end endmodule SR LATCH module sr_latch(input S, input R, output reg Q); always @(*) begin if (S && ~R) Q = 1; else if (~S && R) Q = 0; // S = R = 0: retain state; S = R = 1: undefined end endmodule D FLIP FLOP module d_ff(input D, input clk, output reg Q); always @(posedge clk) begin Q <= D; end endmodule SR FLIP FLOP module sr_ff(input S, input R, input clk, output reg Q); always @(posedge clk) begin if (S && ~R) Q <= 1; else if (~S && R) Q <= 0; end endmodule TOGGLE FLIP FLOP module t_ff(input T, input clk, output reg Q); always @(posedge clk) begin if (T) Q <= ~Q; end endmodule SHIFT REGISTER 8BIT module shift_reg(input clk, input reset, input shift_en, input D, output reg [7:0] Q); always @(posedge clk or posedge reset) begin if (reset) Q <= 0; else if (shift_en) Q <= {Q[6:0], D}; end endmodule BINARY COUNTER 4BIT module binary_counter(input clk, input reset, output reg [3:0] count); always @(posedge clk or posedge reset) begin if (reset) count <= 0; else count <= count + 1; end endmodule BCD COUNTER 0-9 module bcd_counter(input clk, input reset, output reg [3:0] count); always @(posedge clk or posedge reset) begin if (reset) count <= 0; else if (count == 9) count <= 0; else count <= count + 1; end endmodule BINARY ADDER 4BIT module binary_adder(input [3:0] A, input [3:0] B, input Cin, output [3:0] Sum, output Cout); assign {Cout, Sum} = A + B + Cin; endmodule BINARY SUBTTRACTOR 4BIT module binary_subtractor(input [3:0] A, input [3:0] B, output [3:0] Diff, output Bout); assign {Bout, Diff} = A - B; endmodule N TO 1 MUX (EX 4 to 1) module mux4to1(input [3:0] in, input [1:0] sel, output reg out); always @(*) begin case (sel) 2'b00: out = in[0]; 2'b01: out = in[1]; 2'b10: out = in[2]; 2'b11: out = in[3]; endcase end endmodule M to 2^M DECODER (EX 2 to 4) module decoder2to4(input [1:0] in, output reg [3:0] out); always @(*) begin out = 4'b0000; out[in] = 1; end endmodule 2^m-to-m Priority Encoder module priority_encoder4to2(input [3:0] in, output reg [1:0] out); always @(*) begin casez (in) 4'b1???: out = 2'b11; 4'b01??: out = 2'b10; 4'b001?: out = 2'b01; 4'b0001: out = 2'b00; default: out = 2'b00; endcase end endmodule n-word x m-bit Synchronous ROM (example: 8x8) module sync_rom(input clk, input [2:0] addr, output reg [7:0] data); reg [7:0] memory [0:7] = {8'hAA, 8'hBB, 8'hCC, 8'hDD, 8'h11, 8'h22, 8'h33, 8'h44}; always @(posedge clk) begin data <= memory[addr]; end endmodule n-word x m-bit Asynchronous ROM (example: 8x8) module async_rom(input [2:0] addr, output [7:0] data); reg [7:0] memory [0:7] = {8'hAA, 8'hBB, 8'hCC, 8'hDD, 8'h11, 8'h22, 8'h33, 8'h44}; assign data = memory[addr]; endmodule n-word x m-bit Synchronous RAM (example: 8x8) module sync_ram(input clk, input we, input [2:0] addr, input [7:0] din, output reg [7:0] dout); reg [7:0] memory [0:7]; always @(posedge clk) begin if (we) memory[addr] <= din; dout <= memory[addr]; end endmodule Made with nCreator - tiplanet.org
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